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ATmega128
Figure 16. External Data Memory Cycles with SR W n1 = 1 and SR W n0 = 1 (1)
T1
T2
T3
T4
T5
T6
T7
System Clock (CLK CPU )
ALE
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
Prev. data
Prev. data
Address
Address
Data
Data
RD
Note:
1. SR W n1 = SR W 11 (upper sector) or SR W 01 (lower sector), SR W n0 = SR W 10 (upper sector) or
SR W 00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
XMEM Register
Description
MCU Control Register
– MCUCR
Bit
Read/ W rite
Initial Value
7
SRE
R/ W
0
6
SRW10
R/ W
0
5
SE
R/ W
0
4
SM1
R/ W
0
3
SM0
R/ W
0
2
SM2
R/ W
0
1
IVSEL
R/ W
0
0
IVCE
R/ W
0
MCUCR
? Bit 7 – SRE: External SRAM/XMEM Enable
W riting SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, W R, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. W riting SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
? Bit 6 – SRW10: Wait-state Select Bit
For a detailed description in non-ATmega103 compatibility mode, see common description for
the SR W n bits below (XMCRA description). In ATmega103 compatibility mode, writing SR W 10
to one enables the wait-state and one extra cycle is added during read/write strobe as shown in
Figure 14 .
External Memory
Control Register A –
Bit
7
6
5
4
3
2
1
0
XMCRA
Read/ W rite
Initial Value
–
R
0
SRL2
R/ W
0
SRL1
R/ W
0
SRL0
R/ W
0
SRW01
R/ W
0
SRW00
R/ W
0
SRW11
R/ W
0
–
R
0
XMCRA
? Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. W hen writing to this address location, write
this bit to zero for compatibility with future devices.
30
2467X–AVR–06/11
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